The present disclosure relates to semiconductor integrated circuits and, more particularly, to a delay-locked loop (DLL) circuit and a method for generating a multiplied clock therefrom.
DLL circuits are typically used for providing internal clock signals preceding reference clock signals by a predetermined time. Internal clock signals are generally necessary for highly integrated semiconductor circuits, such as Rambus DRAMs or Synchronous DRAMs, which operate in sync with external clock signals corresponding to reference clock signals.
An external clock signal introduced through an input pin is put into a clock buffer. The clock buffer generates an internal clock signal. The internal clock signal controls a data output buffer to output data to an external device. During this operation, the internal clock signal is delayed from the external clock signal in a predetermined time through the clock buffer. The output data from the data output buffer is thereby output after a delay from the internal clock signal by a predetermined time.
Because of that, there is a problem that the output data is output after too long a time following an input of the external clock signal. In other words, it lengthens an output data access time tAC, which is a time for outputting data following an input of an external clock signal.
For the purpose of overcoming the problem of output lateness, a DLL circuit is employed to make an internal clock signal precede a reference clock signal, that is, an external clock signal, in phase by a predetermined time, so that data can be output without a delay from the external clock signal. The DLL circuit receives the external clock signal and then generates the internal clock signal earlier in phase by a predetermined time. The internal clock signal is used in each unit or block, such an internal buffer.
A conventional DLL circuit operates to determine the length of a delay time by means of a voltage signal. For that reason, there is an operational burden that the voltage signal is needed to swing in a large range in order to support a wide range of operating frequencies. Furthermore, with a low driving voltage, there is less change in linearity of an operating frequency along with the voltage signal.